Circuit simulation is one of the most computationally expensive procedures among various design analysis methodologies and techniques, especially when a transistor level circuit with a large number of devices is being analyzed. Recent advances in design and process technology, including increases in computational power, have allowed new and previously unworkable techniques to be used to attack these large scale tasks. Advanced simulation techniques like circuit partitioning were designed to improve the transient analysis run time, while keep accuracy degradation fairly small.
Typically, the number of partitions relates to the number and types of components, the circuit topology, available computing resources, etc. As the number of partitions become very large (e.g., as the circuit size becomes very large), the simulation times may become undesirably long. Thus, it may be desirable to provide techniques for reducing circuit simulation times while preserving simulation accuracy.